Physical blocks which are arranged over a plurality of memory chips are combined to configure a virtual block, thereby achieving read and write accesses to a non-volatile memory, in order to improve the performance using the parallelism of processes or perform the error correction protection of a memory in which an error is likely to occur, when data is written to the non-volatile memory. When the number of normal (good) physical blocks in all chips is sufficient, the physical blocks can be combined such that the number of parallel processes is the maximum in all virtual blocks. However, with the miniaturization of the non-volatile memory, the number of defective blocks (hereinafter, referred to as bad blocks) which are not normally operated in the non-volatile memory has increased due to various causes.
In addition, in some cases, the physical block which has not been a bad block at the initial start of the system changes to the bad block when it is used for a long time. For example, a wear leveling method has been used which controls the number of erasing/writing processes for each block to perform wear leveling for each block. However, it is difficult to completely control the generation of the bad block due to, for example, a difference in durability which depends on finish in a manufacturing process or the position on the chip.
If as many virtual blocks as possible are to be configured by using physical blocks other than bad blocks, a virtual block might be configured by selecting a plurality of physical blocks from the same plane of the same memory chip in some cases. The physical blocks belonging to the same plane of the same memory chip cannot be accessed from a controller at the same time. Therefore, depending on the method of configuring a virtual block, the time required for access varies between virtual blocks.